The present invention relates to a semiconductor device, and more particularly to a module in which at least two semiconductor elements each having a self turn-off function, such as gate turn-off thyristors having a self turn-off function (hereinafter referred to as "GTO's") and transistors are connected in parallel within a package. The above semiconductor element will hereinafter be referred to as "chip".
In a conventional semiconductor device which is disclosed in Japanese Patent Application unexamined publication No. 59-110,146 and in which two chips are connected in parallel within a package, the chips have the same characteristics, the control terminals of the chips are connected directly to each other, and only the chips are made symmetrical with respect to a specified plane within the package. When the semiconductor device performs a high-speed operation, for example, is rapidly turned on, the current flowing through one of the chips is greatly different from the current flowing through the other chip. Such imbalance of current may cause either one of the chips to be damaged. In order to avoid damage to the chip, it is necessary to decrease the rated current of the semiconductor device. Thus, the parallel connection of the chips will reduce the efficiency of the semiconductor device.
In the conventional semiconductor device, the wiring for connecting the chips in parallel within the package has a reactance of about 10.sup.-9 H and a resistance of about 10.sup.-6 .OMEGA.. Such reactance and resistance are negligibly small. Accordingly, the internal wiring for connecting the chips to external terminals which are mounted on the package, is formed in accordance with the positions of the chips in the package and the arrangement of the external terminals, without paying any special attention to the arrangement of the internal wiring.
In recent years, such a semiconductor device is required to perform a high-speed operation, and specifically it is required to turn on or turn off the semiconductor device in a time of the order of microseconds. The inventors have found through experiments that the impedance of internal wiring which has hitherto been neglected, is a very important problem in such a situation.
Now, let us consider a case where two GTO chips are connected in parallel within a package and the difference in ON-voltage between the GTO chips is equal to or less than 0.2 V, by way of example. When the GTO chips are turned on and turned off, the imbalance rate of current at the turn-on time, that is, the ratio of the difference between the turn-on current flowing through one of the GTO chips and the turn-on current flowing through the other GTO chip to the sum of these turn-on currents lies within a range from 0% to 38%. Further, the imbalance rate of current in the stationary ON-state lies within a range from 0% to 5%, and the imbalance rate of current at the turn-off time lies within a range from 0% to 30%.